CS Cracker CSA 151-192 Questions

 
1).    With respect to cache organisation, direct maps each block of main memory into ______ possible cache line.
A).   Four
B).   Only one
C).   Two
D).   Eight
 
2).    Opcodes are represented by abbreviations called:
A).   Mnemonics
B).   Operators
C).   Binary codes
D).   Lexemes
 
3).    The number of lines used in a data bus is referred to as the _______ of the data bus.
A).   Volatility
B).   Width
C).   Density
D).   Length
 
4).    Which of the following is a communication pathway connecting two or more devices of a computer?
A).   Control Unit (CU)
B).   Bus
C).   UPS
D).   Memory
 
5).    The number of addressable memory units for a 10-bit size address bus is
A).   1024
B).   1023
C).   512
D).   256
 
6).    With respect to system buses, SCSI stands for:
A).   Synchronous Computer System Interface
B).   Small Computer Side Interface
C).   Small Computer System Interface
D).   Solid Computer System Interface
 
7).    Which of the following data transfer schemes requires constant monitoring by the CPU of the peripheral devices?
A).   Programmed IO
B).   Both, Interrupt-driven IO and DMA
C).   Interrupt-driven IO
D).   Direct Memory Access (DMA)
 
8).    State whether the following statements are true or false.
        (I)       For main Memory, the unit of transfer is the number of bytes read out of or written into memory at a time.
       (II)       The unit of transfer need not equal a word or an addressable unit.
A).   True, False
B).   False, False
C).   True, True
D).   False, True
 
9).    State whether the following statements are true or false.
        (I)       SCSI is itself a type of bus used to support local disk drives and other peripherals.
       (II)       A serial port could be used to support a printer or scanner.
A).   True, False
B).   False, False
C).   True, True
D).   False, True
 
10). With respect to size, which of the following represents the correct relationships between different categories of cache memory?
A).   L2<L1<L3
B).   L1<L2<L3
C).   L1<L3<L2
D).   L3<L2<L1
 
11). Which of the following sequences of one-address instructions can be used to evaluate?
 Y = (A - B) / (C + D * E)
 
A).   LOAD D
ADD C
MPY E
STORE Y
LOAD A
SUB B
DIV Y
STORE Y
 
B).   LOAD D
MPY E
ADD C
LOAD A
STORE Y
SUB B
DIV Y
STORE Y
 
C).   LOAD D
MPY E
ADD C
STORE Y
LOAD A
DIV Y
STORE Y
 
D).   LOAD D
MPY E
ADD C
STORE Y
LOAD A
DIV Y
SUB B
STORE Y
12). Which of the following sequences of three-address instructions can be used to evaluate?
 Y = (A - B) / (C + D * E)
 
A).   SUB Y, A, B
MPY T, D, E
ADD T, T, C
DIV T, Y, T
 
B).   SUB Y, A, B
ADD T, T, C
MPY T, D, E
DIV Y, Y, T
 
 
C).   SUB Y, A, B
MPY T, D, E
ADD T, T, C
DIV Y, T, T
 
D).   SUB Y, A, B
MPY T, D, E
ADD T, T, C
DIV Y, Y, T
13). Identify the valid cache organisation techniques:
        (I)       Direct
       (II)       Associative
      (III)      Set - Associative
A).   (I), (II) and (III)
B).   (I) and (II) only
C).   (II) and (III) only
D).   (I) and (III) only
 
14). Which of the following determines the time it takes for devices to coordinate the use of the bus?
A).   Propagation delay
B).   Cycle delay
C).   Clock delay
D).   Data transfer delay
 
15). Which of the following refers to a memory access mechanism in which the time to access a given location is constant and independent of the sequence of prior accesses?
A).   Sequential Access
B).   Direct Access
C).   Associative Access
D).   Random Access
 
16). Which of the following statements is correct?
        (I)       A hard disk is also used to provide an extension to the main memory known as virtual memory.
       (II)       DRAM is faster than SRAM
      (III)      External, nonvolatile memory is also referred to as 'Secondary Memory' or 'Auxiliary Memory'.
A).   (I) and (II)
B).   (II) and (III)
C).   (I) and (III)
D).   (I), (II) and (III)
 
17). State whether the following statements are true or false.
        (I)        With one-address instructions, the programmer generally has available only one general-purpose register, the accumulator.
       (II)       Zero-address instructions are applicable to a special memory organization called stack.
A).   Ture, False
B).   False, False
C).   False, True
D).   True, True
 
18). With respect to Peripheral Component Interconnect (PCI), the letter 'e' in PCIe stands for:
A).   Express
B).   Extreme
C).   Excess
D).   Element
 
19). Which respect to accessing speed, which of the following represents the correct relationship between different categories of cache memory?
A).   L2<L1<L3
B).   L3<L2<L1
C).   L1<L2<L3
D).   L1<L3<L2
20). With respect to system bus, ___ are used to control the access to and the use of the data and address lines.
A).   Decoders
B).   Control Lines
C).   Encoders
D).   Address Lines
 
21). Which of the following is NOT a common field found in instruction formats?
A).   An address field
B).   A sign field
C).   A mode field
D).   The opcode field
 
22). Which of the following is a characteristic of a RISC processor?
A).   Large variety of addressing modes
B).   Large number of instructions
C).   Single cycle instruction execution
D).   Variable length instruction formats
 
23). Which of the following modes of transfer is needed for fast devices such as magnetic disks?
A).   Cycle stealing
B).   Programmed transfer
C).   Daisy chaining
D).   Burst transfer
 
24). Which of the following in a microprogrammed control unit is a next address generator?
A).   Micro Program Sequencer
B).   Pipeline Register
C).   Micro Program Controller
D).   Control Address Register
 
25). Which of the following memory units communicates directly with the CPU?
A).   Secondary Memory
B).   Main Memory
C).   Auxiliary Memory
D).   Tertiary Memory
 
26). A memory module with a printed circuit board on which DRAM chips are mounted on both sides is called:
A).   Dual Outline Memory Module (DOMM)
B).   Floating-Gate Metal Oxide Semi-Conductor
C).   Binary Inline Memory Module (BIMM)
D).   Dual Inline Memory Module (DIMM)
 
27). Which of the following is NOT a CPU organisation type with respect to instruction formats?
A).   Stack Organisation
B).   Single Accumulator Organisation
C).   Queue Organisation
D).   General Register Organisation
 
28). In which of the following cache write method for updating main memory, only cache location is updated during write operation?
A).   Write-Front
B).   Write-Up
C).   Write-Back
D).   Write-Through
 
29). Which of the following is NOT an instruction pipeline hazard?
A).   Control Hazard
B).   Structural Hazard
C).   Address Hazard
D).   Data Hazard
 
30). Which of the following in a computer system bus provides a path for the transfer of data between the processor and common memory?
A).   Address lines
B).   Data lines
C).   Timing signals
D).   Control lines
 
31). Which of the following is defined as the memory address obtained from the computation dictated by a given addressing mode?
A).   Effective Address
B).   Interleaved Address
C).   Dedicated Address
D).   Random Address
 
32). Which of the following would be a preferred mode of transfer data between a magnetic disk and the memory?
A).   Programmed I/O
B).   Hardware interrupt driven I/O
C).   Software Interrupt driven I/O
D).   DMA
 
33). 'PUSH A' indicates which of the following instruction format?
A).   Zero Address Instruction (A)
B).   One Address Instruction
C).   Two Address Instructions
D).   Three Address Instructions
 
34). Which of the following micro programmed control unit organisations does NOT need any decoder circuitry to generate the control signals?
A).   Horizontal
B).   Diagonal
C).   Vertical
D).   Interleaved
 
35). A computer has 32 MB memory. How many bits are needed to access any single bytes in the memory?
A).   25
B).   16
C).   24
D).   20
 
36). SSID stands for
A).   Secure service identifier
B).   Secure set independent device
C).   Service set identifier
D).   Service set independent device
 
37). Which of the following does not have 8 data lines?
A).   8085
B).   8086
C).   8088
D).   Z80
 
38). A computer has 128 MB memory. Each word in this computer is of 8 bytes. How many bits are required to address any single word in the memory?
A).   27
B).   24
C).   23
D).   25
 
39). To achieve parallelism, one needs a minimum of
A).   2 processors
B).   3 processors
C).   4 processors
D).   None of the above
 
40). Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. 512 bytes of data are stored in a bit in serial manner in a sector. The capacity of the disk pack and the number of bits required to specify a particular sector in the disk are respectively.
A).   256 MB, 19 bits
B).   256 MB, 28 bits
C).   512 MB, 20 bits
D).   64 MB, 28 bits
 
41). Which of the following is not true regarding registers?
A).   Internal storage of CPU
B).   Can hold either data or instruction
C).   Made up of flip-flop
D).   Cannot store intermediate results
 
42).  While implementing a stack on a register stack, the stack pointer register is
A).   Incremented first during push operation
B).   Decremented first during push operation
C).   Incremented first during pop operation

D).   Decremented first during pop operation